Many digital circuits, such as memory circuits, receive a reference clock from a host device to operate. Such circuits often employ an off-chip driver (OCD) to transfer output data to the host device. Due to propagation delays through the OCD and other circuit elements, timing differences may exist between the circuit and the host device so that the output data may not be aligned with the reference clock. To remedy this problem, delay locked loops (DLLs) are often employed to compensate for these timing differences so that output data from the OCD is aligned with the reference clock.
Memory circuits often operate in a differential environment with the reference clock comprising a clock signal and an inverted clock signal, with circuit timing being based on the rising edges of the clock and inverted clock signals. One conventional DLL employed by such a memory circuit delays the clock and inverted clock signals with a pair of adjustable delay elements to generate and provide an output clock to the off-chip driver so that output data is aligned with the reference clock. The delay elements are adjusted to compensate for memory circuit propagation delays (e.g. OCD and data path propagation delays) so as to maintain a desired phase relationship between the rising edges of the clock and inverted clock signals within the memory circuit.
In addition to aligning output data with the host reference clock, it is also important for a memory circuit to have a clock signal with a duty cycle of approximately fifty percent. This provides the memory circuit with approximately an equal amount of time on the high level phase and the low level phase for transferring data into and out of the memory circuit. However, reference clocks sometimes deviate from a 50% duty cycle. To address this problem, memory circuits generally employ duty cycle correctors (DCCs) adjust and maintain clock signals at a fifty percent duty cycle. One conventional DCC employs a pair of delay elements to delay both the clock and inverted clocks signals and adjusts one of the delay elements to maintain transitions between rising edges of the clock and inverted clock signals at approximately one-half a clock cycle.
To achieve output alignment with a host device and a clock duty cycle of fifty percent, memory and other circuits often employ a DLL and a DCC positioned in series with one another. While functionally effective, such configurations, particularly the variable delay elements, consume a large amount of space on an integrated circuit.